The evolution of integrated circuits has seen a continuing decrease in the size of features that are fabricated in and on semiconductor wafers. Photolithographic processes are one of many fabrication steps critical in forming such small feature size structures. Conventional photolithographic techniques include forming a layer of energy sensitive resist over a material stack formed on a substrate. An image of a pattern is introduced into the energy sensitive resist layer by directing radiation through an appropriately patterned photomask. The substrate is then exposed to a chemical etchant to transfer the pattern introduced into the energy sensitive resist layer into one or more layers of the material stack. The chemical etchant is selected to have a greater etch selectivity for the material layers of the stack than for the energy sensitive resist. That is, the chemical etchant etches the one or more layers of the material stack at a faster rate than it etches the energy sensitive resist. The faster etch rate for the one or more material layers of the stack typically prevents the energy sensitive resist material from being consumed prior to completion of the pattern transfer.
Photolithographic processes used in the manufacture of many modern integrated circuits (e.g., integrated circuits having minimum features sizes of about 0.35 microns or less) employ deep ultraviolet (DUV) imaging wavelengths (e. g., wavelengths of 248 nm or 193 nm) to generate the resist patterns. The DUV imaging wavelengths improve resist pattern resolution because diffraction effects are reduced at these shorter wavelengths. The increased reflective nature of many underlying materials (e. g., polysilicon and metal silicides) at such DUV wavelengths, however, may degrade the resulting resist patterns.
One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC suppresses the reflections off the underlying material layer during resist imaging, providing accurate pattern replication in the layer of energy sensitive resist.
Layers of inorganic material such as silicon oxynitride, titanium nitride and others have been predominately used by the industry as ARCs for deep UV radiation. One problem with such ARCs, however, is that amines (NH2 groups) may form on the surface of the layer. The exposure of photoresists that are typically used with deep UV radiation generally creates an acidic reaction in the photoresist. The resulting acid compounds then react with the developer to create a mask. Since the amines formed at the surface of the inorganic ARC layer are basic, they tend to neutralize the acids generated by the exposure of the photoresist and thereby limit the development of the photoresist. This problem, which is often referred to as “resist poisoning” or “footing” may result in small foot-like portions of resist that are left undeveloped near the interface between the ARC and resist and ultimately interfere with the patterning of features underneath the photoresist.
A variety of different techniques have been developed to address the footing issue. One technique devised minimizes or eliminates the formation of amines at the ARC/photoresist interface by forming a silicon dioxide cap layer over the ARC before the photoresist is deposited. Another technique reduces amine formation by exposing the ARC to a plasma of reactive oxygen species prior to forming the photoresist layer. Basically, it is believed that exposure to reactive oxygen forms a thin layer of SiO2 at the surface of the ARC which prevents amines from migrating into the subsequently deposited photoresist material.
Despite the development of these and other techniques to reduce footing, there are some situations in which new techniques to minimize resist poisoning are desirable. For example, FIGS. 1A-1D illustrate an exemplary damascene etch sequence that is commonly used in the formation of integrated circuits having copper signal lines. In FIG. 1A a dielectric layer 12 is formed over a substrate 10. As shown in subsequent figures, dielectric layer 12 will have a via and a signal line trench formed in it as part of the interconnect structure of an integrated circuit. An ARC 14 is formed over dielectric layer 12 and a thin oxide layer 16 is created on the surface of ARC 14. A photoresist layer 18 is formed over ARC 14 and patterned according to a via pattern 20.
In FIG. 1B the via pattern 20 is transferred into dielectric layer 12 using any appropriate etch sequence as is known to those of skill in the art. This etch step also removes a portion of photoresist layer 18 as shown in FIG. 1B. Next, photoresist layer 18 is stripped and a new photoresist layer 22 is formed over the substrate. As shown in FIG. 1C, photoresist layer 22 fills the partially etched via and contacts sidewall areas 24 of ARC 14.
Next, photoresist layer 22 is patterned according to a trench pattern. As shown in FIG. 1D, however, amines migrate from the sidewall of ARC 14 into photoresist layer 22 interfering with the development of the layer. The resulting developed structure may include undeveloped regions of photoresist along the sidewalls of the initially etched via pattern as shown by photoresist portions 26 in FIG. 1D. In some instances the area of undeveloped resist may be sufficiently large to form a bubble 27 as shown in dashed lines.
Accordingly, new and different techniques of forming ARC layers are desirable.